One of the elementary operations in computing systems is multiplication. Therefore, high-speed and low-power multipliers design is mandatory for
efficient computing systems. In designing low-energy dissipation circuits, reversible logic is more efficient than irreversible logic circuits but at the cost of higher
complexity. This paper introduces an efficient signed/unsigned 4 × 4 reversible
Vedic multiplier with minimum quantum cost. The Vedic multiplier is considered
fast as it generates all partial product and their sum in one step. This paper proposes two reversible Vedic multipliers with optimized quantum cost and garbage
output. First, the unsigned Vedic multiplier is designed based on the Urdhava Tiryakbhyam (UT) Sutra. This multiplier consists of bitwise multiplication and adder
compressors. Compared with Vedic multipliers in the literature, the proposed
design has a quantum cost of 111 with a reduction of 94% compared to the previous design. It has a garbage output of 30 with optimization of the best-compared
design. Second, the proposed unsigned multiplier is expanded to allow the multiplication of signed numbers as well as unsigned numbers. Two signed Vedic multipliers are presented with the aim of obtaining more optimization in performance
parameters. DesignI has separate binary two’s complement (B2C) and MUX circuits, while DesignII combines binary two’s complement and MUX circuits in
one circuit. DesignI shows the lowest quantum cost, 231, regarding state-ofthe-art. DesignII has a quantum cost of 199, reducing to 86.14% of DesignI.
The functionality of the proposed multiplier is simulated and verified using XILINX ISE 14.2. |
