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Dr. Eslam Yahya :: Publications: |
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| Title: | Efficient modular-pipelined AES implementation in counter mode on ALTERA FPGA |
| Authors: | François Charot, Eslam Yahya, Charles Wagner |
| Year: | 2003 |
| Keywords: | Not Available |
| Journal: | Not Available |
| Volume: | Not Available |
| Issue: | Not Available |
| Pages: | Not Available |
| Publisher: | Not Available |
| Local/International: | International |
| Paper Link: | Not Available |
| Full paper | Not Available |
| Supplementary materials | Not Available |
| Abstract: |
Abstract This paper describes a high performance single-chip FPGA implementation of the new Advanced Encryption Standard (AES) algorithm dealing with 128-bit data/key blocks and operating in Counter (CTR) mode. Counter mode has a proven-tight security and it enables the simultaneous processing of multiple blocks without losing the feedback mode advantages. It also gives the advantage of allowing the use of similar hardware for both encryption and decryption parts. The proposed architecture is modular. The architecture ... |
