Publications of Benha University on Google Scholar: Formal semantics of VHDL timing |
| Title: | Formal semantics of VHDL timing |
| Authors: | A Salem, D Borrione |
| Year: | 2012 |
| Keywords: | Not Available |
| Journal/Conference: | VHDL for Simulation, Synthesis and Formal Proofs of Hardware |
| Volume: | 183 |
| Issue: | Not Available |
| Pages: | Not Available |
| Publisher: | VHDL for Simulation, Synthesis and Formal Proofs of Hardware 183, 195 |
| URL on Google: | https://scholar.google.com.eg/citations?view_op=view_citation&hl=en&citation_for_view=QCRKlN4AAAAJ:3s1wT3WcHBgC |
| Citations: | Not Available |
| Paper Link: | Not Available |
| Full paper | Not Available |