| Title: |
Formal verification of VHDL descriptions in Boyer-Moore: First results |
| Authors: |
D Borrione, L Pierre, A Salem |
| Year: |
1992 |
| Keywords: |
Not Available |
| Journal/Conference: |
VHDL for Simulation, Synthesis and Formal Proofs of Hardware, |
| Volume: |
Not Available |
| Issue: |
Not Available |
| Pages: |
227-243 |
| Publisher: |
VHDL for Simulation, Synthesis and Formal Proofs of Hardware, 227-243 |
| URL on Google: |
https://scholar.google.com.eg/citations?view_op=view_citation&hl=en&citation_for_view=QCRKlN4AAAAJ:eQOLeE2rZwMC |
| Citations: |
6 |
| Paper Link: |
Not Available |
| Full paper |
Not Available |
|
